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Flash Memory SIMM
of the Flash SIMM presence-detect lines (see Table 5-10), the debugger can establish (via
register OR0 in case CS0 is used or OR4 if CS4 is used) the correct number of wait-states
needed to access the Flash SIMM (considering 100MHz system clock frequency).
The control over the Flash is done with the GPCM and a dedicated CS0 (or CS4) region
which controls the whole bank. During hard - reset initialization 1 , the debugger or any
application S/W for that matter, reads the Flash Presence-Detect lines via BCSR and
determines how to program registers BR0 & OR0 (or BR4 & OR4), within which the size
and the delay of the region are determined.The Flash module may be disabled / enabled at
any time by writing ’1’ /’0’ respectively to the FlashEn bit in BCSR1. The Flash connection
scheme is shown in Figure 5-6.
.
FLASH SIMM
DATA(0:31)
ADDRESS(7:29)
WE0
WE1
WE2
WE3
D(31:0)
A(22:0)
WE0
WE1
WE2
WE3
BCSR
POE
POE
CS0
CS4
FLASH
CS
CS1
CS2
CS3
CS4
PD1
PD2
PD3
PD4
PD5
PD6
PD7
CS1
CS2
CS3
CS4
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Figure 5-6. FLASH SIMM Connection Scheme
1 i.e.,
initialization that follow the hard reset sequence at system boot.
MPC8272ADS User Guide
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